DIGITAL LOGIC DESIGN

Unit-I

Algebra of logical variables: Review of Boolean algebric theorems, Realization of Boolean function and sufficiently of NAND/NOR for implemenation stand SOP and POS forms of logical functions, Minimisation techniques using K-Map and Quine Mcclus key method (upto 6 varables). Logic familes: Basic TTL, NAND with totem pole o/p and open collector O/P. Tristate O/P, I/P parameters: Fan-in,fan-out,noise margin, propagation delay, power dissipation STTL, LSTTL, CMOS characterstics:CMOS NAND/NOR, CMOS ,comparision of different logic families.

Unit-II

Design of combinational logic circuits:Delay in combinational logic circuits, adders, substractors, decoders, encoders and parity encoders,three-state gates, gate array-ROMs, PLAs and PALs, MOS statiac RAM, dynamic RAM, refreshing memory cycles. Designing with ROMs, Designing with PLAs, Designing with PALs, seven segment displays, An error encoding and decoding system. BCD adder/subtractor using 7483,74181 ALU, code converter- binary,BCD,Excesss-3,Gray,parity generator and checker, implementation of Boolean functions using MUX, DEMUX.

Unit-III

Flip flops, Registers, Counters: One bit latch using NOR/NAND, steered latches, S-R FF , clocked S-R , J-K , race around condition , M/S J-K FF , D FF , T FF , Shift registers:SISO,SIPO,PISO,PIPO,Desig of synchronous and Asynchronous counters,counter ICs like 7490,7492,7493,74162,74191,Functional block diagram of frequency counters. State variables and excitation variables, state diagram representation , Moore and Melay circuits , design of sequence generator and sequence detector , elimination of redundant states , Avoiding lockouts , fundamental mode sequential circuits , elimination of critical race , hazards , pulse mode sequential circuits.

Unit-IV

Algorithm State Machines : ASM charts , notations,design of simple controller , Multiplier controller method , RTL notations and implementation.

Unit-V

Programmable Logic Devices : Programmable Logic elements and array logic , Implementation of combinational and sequential logic designing using PLEs , PALs , Introduction to FPGA.